In a lead-frame-based semiconductor package, a chip is mounted on a die pad of the lead frame, and electrically connected to leads of the lead frame by means of a plurality of bonding wires; alternatively, the chip can be mounted on and wire-bonded to the leads without having to form a die pad for the lead frame. Wire-bonding technology, however, induces several problems. Relatively long bonding wires may be unfavorable to quality of electrical connection between the chip and the lead frame; during a molding process for chip encapsulation, the bonding wires are subject to mold-flow impact that may easily cause wire sweeping or sagging, making adjacent bonding wires undesirably come into contact with each other and short-circuited. Moreover, the semiconductor package needs to be dimensioned for comfortably accommodating loop height of the bonding wires, such that overall package height is hard to be effectively reduced thereby not in favor of profile miniaturization.
Flip-chip semiconductor packages adopts an advanced package technology for facilitating profile miniaturization and high integration and performances. A flip-chip semiconductor package is characterized by mounting a chip on a chip carrier such as a substrate in a flip-chip manner, wherein an active surface, where electronic components or circuits are formed, of the chip faces toward the chip carrier and is electrically connected to the chip carrier by solder bumps interposed between the active surface of the chip and the chip carrier. Such an electrical-connection method is more beneficial than wire-bonding technology without concerning the above-mentioned problems generated in the use of bonding wires. However, as the solder bumps are usually made of soft metal such as tin 63/lead 37 alloy having a low melting point, during a reflow-soldering process, the solder bumps may over-collapse and hardly resist thermal stress generated by CTE (coefficient of thermal expansion) mismatch in materials between the chip and the chip carrier; this thereby undesirably damages electrical connection between the chip and the chip carrier. Moreover, the flip-chip arrangement requires the solder bumps to be precisely bonded to the chip carrier, which thus increases fabrication costs and is normally applied to high-level products, but not suitable for lead-frame-based structures that accommodates DRAM (dynamic random access memory) or SRAM (static random access memory) chips.
Accordingly, U.S. Pat. No. 5,331,235 teaches a flip-chip semiconductor package with a lead frame as a chip carrier. As shown in FIG. 1, in this flip-chip semiconductor package, the lead frame 37 is double-side mounted with two chips 32, 34, wherein the chips 32, 34 are respectively electrically connected to the lead frame 37 by means of solder bumps 33, 35 bonded to a TAB (tape automated bonding) tape 31 for the sake of miniaturization in package profile. However, the use of the TAB tape 31 would undesirably increase fabrication costs, and the solder bumps 33, 35 may still over-collapse to impair electrical connection between the chips 32, 34 and the lead frame 37.
In response to electrical-connection problems, U.S. Pat. No. 6,184,573 discloses a flip-chip semiconductor package having a lead frame being applied with a solder mask. As shown in FIG. 2, in this flip-chip semiconductor package, the solder mask 26 is applied over leads 27, and formed with a plurality of openings 260 corresponding in position to solder bumps 24, 25 respectively implanted on chips 21, 22 that are to be mounted on the leads 27. During a reflow-soldering process, the solder bumps 24, 25 are wetted to the openings 260 without over-collapsing or over-wetted to other unintended area of the leads 27, so as to assure electrical connection between the chips 21, 22 and the leads 27 by means of the solder bumps 24, 25. However, fabricating processes for coating the solder mask 27 and forming the openings 260 are relatively complex and cost-ineffective to implement.
Therefore, the problem to be solved is to provide a flip-chip semiconductor package, which can be cost-effectively fabricated, and allows a chip to be well electrically connected to a chip carrier by means of solder bumps.